1. Field of Invention
The present invention pertains to the field of computer systems. More particularly, this invention relates to data transfer operations for peripherals in a computer system.
2. Art Background
Prior computer systems typically include a host processor and a host memory along with a variety of input/output (I/O) peripherals. Such I/O peripherals may comprise, for example, I/O controllers for mass storage devices and network interfaces. Prior computer systems typically include one or more buses such as host buses, specialized I/O buses or peripheral buses that enable communication between a host processor and the I/O peripherals.
One prior method for transferring information to an I/O peripheral via such buses may be referred to as programmed I/O or slave cycles. Typically, such programmed I/O is performed by a host processor. Such a host processor usually transfers a data block from a host memory to the I/O peripheral by employing a series of read cycles and write cycles on such buses. Such programmed I/O operations usually consume a relatively large number of host processor cycles if the data blocks consumed by an I/O peripheral are relatively large. Unfortunately, such excessive consumption of host processor cycles typically slows other operations in the computer system.
Another prior method for transferring information to an I/O peripheral may be referred to as direct memory access (DMA). Such DMA transfers are usually performed by DMA circuitry that is external to the host processor. Typically, the host processor provides the address and length of the data block contained in host memory to the DMA circuitry. The DMA circuitry then usually arbitrates for control of the host bus or I/O bus and obtains control as a bus master. The DMA circuitry then reads the data block directly from the host memory while the host processor is free to perform other tasks.
Prior I/O peripherals such as disk controllers or network controllers that consume relatively large data blocks commonly employ DMA data transfers because DMA operations are usually more efficient than programmed I/O operations. For example, the transfer of a data word using programmed I/O usually requires two bus cycles by the host processor including a read from host memory and a write to the I/O peripheral. A DMA operation, on the other hand, typically includes only one bus transaction per data word which is a direct read from the host memory by the I/O peripheral. In addition, some prior computer systems include I/O buses that enable special burst data transfers during such DMA operations. Such burst data transfers typically enable the transfer of multiple data words in quick succession to an I/O peripheral.
Prior I/O peripherals are usually managed by hardware dependent driver routines that execute on a host processor. Typically, an operating system executing on a host processor calls a driver routine to manage a particular I/O peripheral and to perform data transfers to that I/O peripheral.
In addition, prior host processors commonly implement a memory management mechanism that maps the limited address space of the host memory to a virtual address space for the host processor. The operating system and driver routines typically reference data blocks stored in the host memory with virtual addresses. I/O peripherals, on the other hand, usually reference data blocks stored in the host memory with physical addresses rather than virtual addresses.
As a consequence, prior driver routines typically convert the virtual addresses of data blocks stored in host memory into physical addresses which are used by the I/O peripheral. Such a driver routine usually converts a virtual address to a physical address by calling an operating system routine that translates virtual addresses to physical addresses. In addition, such a driver routine commonly calls operating system routines that lock output data blocks into the host memory which prevents paging operations on the output data blocks during DMA operations.
Unfortunately, such virtual to physical address translations and memory page locking operations consume time and usually delay the start of a DMA operation. Such delays in the start of a DMA operation typically slow the overall data output performance of such I/O peripherals.